1. Field of the Invention
This invention relates to a semiconductor device.
2. Description of Related Art
In recent years, with miniaturization of electronic equipment embedding semiconductor devices or the like, demand for fining of the semiconductor devices has been intensifying. Therefore, development of the semiconductor devices advances in which a plurality of semiconductor chips are stacked over and the plurality of semiconductor chips are connected via penetration electrodes.
In general, in the semiconductor device in which the plurality of semiconductor chips are stacked over, in order to prevent bumps for connecting the semiconductor chips from rupturing resulting from a warp of the semiconductor chip, dummy bumps or reinforcing bumps (which will later be called “dummy bumps” also including the reinforcing bumps) are formed on each semiconductor chip (see, JP-A 2010-161102 which will be called Patent Document 1 and which corresponds to US 2010/0171208 A1).
However, in a case where semiconductor chips having different sizes such as a logic chip and a memory chip of Patent Document 1 are stacked over, dummy bumps formed on one semiconductor chip may be positioned to edges (edge portions) of another semiconductor chip and it is feared that crack occurs in the edge portions of the other semiconductor chip in the manner which will later be described in conjunction with FIGS. 9A and 9B.